View ADM800MARNZ_9007234.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

rev. 0 information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of analog devices. a adm691a/adm693a/adm800l/m one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 617/329-4700 world wide web site: http://www.analog.com fax: 617/326-8703 ? analog devices, inc., 1996 microprocessor supervisory circuits functional block diagram chip enable output control v batt v cc ce in osc in osc sel watchdog input (wdi) power fail input (pfi) 1 voltage detector = 4.4v (adm693a/adm800m) adm691a/adm693a adm800l/adm800m 1.25v watchdog timer reset & watchdog timebase reset & generator 4.65v 1 batt on low line v out ce out reset reset watchdog output ( wdo ) power fail output ( pfo ) watchdog transition detector features low power consumption: precision voltage monitor 6 2% tolerance on adm800l/m reset time delay200 ms, or adjustable 1 m a standby current automatic battery backup power switching fast onboard gating of chip enable signals also available in tssop package (adm691a) applications microprocessor systems computers controllers intelligent instruments automotive systems critical m p power monitoring general description the adm691a/adm693a/adm800l/adm800m family of supervisory circuits offers complete single chip solutions for power supply monitoring and battery con trol functions in microprocessor systems. these functions include m p reset, backup-battery switchover, watchdog timer, cmos ram write protection, and power-failure warning. the family of products provides an upgrade for the max691a/93a/800m family of products. all parts are available in 16-pin dip and so packages. the adm691a is also available in a space-saving tssop package. the following functionality is provided: 1. power-on reset output during power-up, power-down and brownout conditions. the circuitry remains operational with v cc as low as 1 v. 2. battery backup switching for cmos ram, cmos micro- processor or other low power logic. 3. a reset pulse if the optional watchdog timer has not been toggled within a specified time. 4. a 1.25 v threshold detector for power fail warning, low bat- tery detecti on, or to m onitor a power supply other than +5 v. v batt v cc cmos ram ce in osc in osc sel bat on low line v out ce out reset reset pfo wdi v cc wdo i/o line nmi a0?15 ? power ? address decode adm691a adm693a adm800l adm800m gnd pfi battery 0.1? +5v nc r2 r1 input power 7805 system status indicators figure 1. typical application
adm691a/adm693a/adm800l/mCspecifications C2C rev. 0 (v cc = 4.75 v to 5.5 v (adm691a, adm800l) 4.5 v to 5.5 v (adm693a, adm800m) v batt = +2.8 v, t a = t min to t max unless otherwise noted) parameter min typ max unit test conditions/comments battery backup switching v cc , v batt operating voltage range 0 5.5 v v out output voltage v cc C 0.05 v cc C 0.02 v i out = 25 ma v cc C 0.3 v cc C 0.2 v i out = 250 ma v cc to v out output resistance 0.8 1.2 w v cc = 4.5 v v out in battery backup mode v batt C 0.3 v v batt = 4.5 v, i out = 20 ma v batt C 0.25 v v batt = 2.8 v, i out = 10 ma v batt C 0.15 v v batt = 2.0 v, i out = 5 ma v batt to v out output resistance 12 w v batt = 4.5 v 20 w v batt = 2.8 v 25 w v batt = 2.0 v supply current (excludes i out ) 70 100 m av cc > (v batt C 1 v) supply current in b. backup (excludes i out ) 0.04 1 m av cc < (v batt C 1.2 v), v batt = 2.8 v battery standby current 5.5 v > v cc > v batt + 0.2 v (+ = discharge, C = charge) C0.1 +0.02 m a(v batt +0.2 v) < v cc , t a = +25 c C1.0 +0.02 m a(v batt +0.2 v) < v cc battery switchover threshold v batt + 0.03 v power up v cc Cv batt v batt C 0.03 v power down battery switchover hysteresis 60 mv batt on output voltage low 0.1 0.4 v i sink = 3.2 ma 0.7 1.5 v i sink = 25 ma batt on output short circuit current 60 ma sink current 1 15 100 m a source current reset and watchdog timer reset voltage threshold adm691a, adm800l 4.5 4.65 4.75 v adm693a, adm800m 4.25 4.40 4.50 v adm800l, v cc falling 4.55 4.70 v t a = +25 c adm800m, v cc falling 4.3 4.45 v t a = +25 c reset threshold hysteresis 15 mv v cc to reset delay 80 m s power down low line to reset delay 800 ns reset timeout period internal oscillator 140 200 280 ms power up reset timeout period external clock 2048 cycles power up watchdog timeout period, internal oscillator 1.0 1.6 2.25 s long period 70 100 140 ms short period watchdog timeout period, external clock 4096 cycles long period 1024 cycles short period minimum wdi input pulse width 100 ns v il = 0.4, v ih = 0.75 v cc reset output voltage 0.004 0.3 v i sink = 50 m a, v cc = 1 v, v batt = 0 v 0.1 0.4 v i sink = 3.2 ma, v cc = 4.25 v 3.5 v i source = 1.6 ma, v cc = 5 v reset output short circuit current 7 20 ma reset output voltage low 0.1 0.4 v i sink = 3.2 ma low line output voltage 0.4 v i sink = 3.2 ma, v cc = 4.25 v 3.5 v i source = 1 m a, v cc = 5 v low line short circuit source current 1 15 100 m a wdo output voltage 0.4 v i sink = 3.2 ma, v cc = 4.25 v 3.5 v i source = 500 m a, v cc = 5 v wdo short circuit source current 3 10 ma wdi input threshold logic low 0.8 v logic high 0.75 v cc v wdi input current C50 C10 m a wdi = 0 v 20 50 m a wdi = v out power fail detector pfi input threshold adm69xa 1.2 1.25 1.3 v v cc = 5 v pfi input threshold adm800l/m 1.225 1.25 1.275 v v cc = 5 v pfi input current 0.01 25 na pfo output voltage 0.4 v i sink = 3.2 ma 3.5 i source = 1 m a pfo short circuit source current 1 15 100 m a pfi to pfo delay 25 m sv in = C20 mv 60 m sv in = 20 mv
C3C rev. 0 adm691a/adm693a/adm800l/m parameter min typ max units test conditions/comments chip enable gating ce in leakage current 0.005 1 m a disable mode ce in to ce out resistance 40 150 w enable mode ce i n to ce out propagation delay 6 10 ns r in = 50 w , c load = 50 pf ce out short-circuit current 0.1 0.75 2.0 ma disable mode, ce out = 0 v ce out output voltage 3.5 v v cc = 5 v, i out = C100 m a 2.7 v v cc = 0 v, v batt = 2.8 v, i out = 1 m a reset to ce out propagation delay 12 m s power down oscillator osc in input current 0.1 5 m a osc sel = 0 v osc in input pullup current 10 100 m a osc sel = v out or floating osc sel input pullup current 10 100 m a osc sel = 0 v osc in frequency range 500 khz osc sel = 0 v osc in threshold voltage v out C 0.4 v out C 0.6 v v ih 3.65 2.00 v v il osc in frequency with ext capacitor 100 khz osc sel = 0 v, c osc = 47 pf notes 1 either v cc or v batt can be 0 v if the other > +2.0 v. specifications subject to change without notice. absolute maximum ratings* (t a = 25 c unless otherwise noted) v cc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . C0.3 v to +6 v v batt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . C0.3 v to +6 v all other inputs . . . . . . . . . . . . . . . . . C0.3 v to v out + 0.5 v input current v cc (peak) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1000 ma v cc (continuous) . . . . . . . . . . . . . . . . . . . . . . . . . . . 250 ma v batt (peak) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 250 ma v batt (continuous) . . . . . . . . . . . . . . . . . . . . . . . . . . 25 ma gnd, batt on . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 ma digital output current . . . . . . . . . . . . . . . . . . . . . . . . . 25 ma power dissipation, n-16 dip . . . . . . . . . . . . . . . . . . 842 mw q j a thermal impedance . . . . . . . . . . . . . . . . . . . . . 135 c/w power dissipation, r-16 narrow soic . . . . . . . . . . . 700 mw q ja thermal impedance . . . . . . . . . . . . . . . . . . . . . . . 110 w power dissipation, r-16 wide soic . . . . . . . . . . . . . 762 mw q ja thermal impedance . . . . . . . . . . . . . . . . . . . . . 110 c/w power dissipation, ru-16 tssop . . . . . . . . . . . . . . 500 mw q ja thermal impedance . . . . . . . . . . . . . . . . . . . . . 158 c/w operating temperature range industrial (a version) . . . . . . . . . . . . . . . . C40 c to +85 c lead temperature (soldering, 10 sec) . . . . . . . . . . . . +300 c vapor phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . . . . 215 c infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . . . +220 c storage temperature range . . . . . . . . . . . . C65 c to +150 c *stresses above those listed under absolute maximum ratings may cause perma- nent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. exposure to absolute maximum ratings for extended periods of time may affect device reliability. table i. product selection table power on low v cc watchdog battery backup base drive chip enable part no. reset time threshold timeout switching ext pnp signals adm691a 200 ms or adj. 4.65 v 3% 100 ms, 1.6 s, adj. yes yes yes adm693a 200 ms or adj. 4.4 v 3% 100 ms, 1.6 s, adj. yes yes yes adm800m 200 ms or adj. 4.4 v 2% 100 ms, 1.6 s, adj. yes yes yes adm800l 200 ms or adj. 4.65 v 2% 100 ms, 1.6 s, adj. yes yes yes ordering guide temperature package model range option adm691aan C40 c to +85 c n-16 adm691aarn C40 c to +85 c r-16n adm691aarw C40 c to +85 c r-16w adm691aaru C40 c to +85 c ru-16 adm693aan C40 c to +85 c n-16 adm693aarn C40 c to +85 c r-16n adm693aarw C40 c to +85 c r-16w adm800lan C40 c to +85 c n-16 adm800larn C40 c to +85 c r-16n adm800larw C40 c to +85 c r-16w adm800man C40 c to +85 c n-16 adm800marn C40 c to +85 c r-16n adm800marw C40 c to +85 c r-16w
adm691a/adm693a/adm800l/m C4C rev. 0 pin descriptions pin mnemonic function 1v batt backup battery input. connect to external battery or capacitor. connect to ground if a backup battery is not used. 2v out output voltage, v cc or v batt is internally switched to v out depending on which is at the highest poten- tial. when v cc is higher than v batt and is also higher than the reset threshold, v cc is switched to v out . when v cc is lower than v batt and below the reset threshold, v batt is switched to v out . connect v out to v cc if a backup battery is not being used. 3v cc power supply input; +5 v. 4 gnd 0 v. ground reference for all signals. 5 batt on logic output. batt on goes high when v out is internally switched to the v batt input. it goes low when v out is internally switched to v cc . the output may also be used to drive the base (via a resistor) of an ex- ternal pnp transistor to increase the output current above the 250 ma rating of v out . 6 low line logic output. low line goes low when v cc falls below the reset threshold. it returns high as soon as v cc rises above the reset threshold. 7 osc in oscillator logic input. with osc sel high or floating, the internal oscillator is enabled and sets the reset delay and the watchdog timeout period. connecting osc in low selects 100 ms while leaving it floating selects 1.6 sec. with osc sel low, osc in can be driven by an external clock signal or an external ca- pacitor can be connected between osc in and gnd. this sets both the reset active pulse timing and the watchdog timeout period. (see table ii and figure 4.) 8 osc sel logic oscillator select input. when osc sel is unconnected (floating) or driven high, the internal oscil- lator sets the reset active time and watchdog timeout period. when osc sel is low, the external oscillator input, osc in, is enabled. osc sel has a 10 m a internal pullup. 9 pfi power fail input. pfi is the noninverting input to the power fail comparator. when pfi is less than 1.25 v, pfo goes low. connect pfi to gnd or v out when not used. 10 pfo power fail output. pfo is the output of the power fail comparator. it goes low when pfi is less than 1.25 v. 11 wdi watchdog input. wdi is a three level input. if wdi remains either high or low for longer than the watch- dog timeout period, reset pulses low and wdo goes low. the timer resets with each transition on the wdi line. the watchdog timer may be disabled if wdi is left floating or is driven to midsupply. 12 ce out output. ce out goes low only when ce in is low and v cc is above the reset threshold. if ce in is low when reset is asserted, ce out will remain low for 15 m s or until ce in goes high, whichever occurs first. 13 ce in chip enable input. the input to the ce gating circuit. connect to gnd or v out if not used. 14 wdo logic output. the watchdog output, wdo , goes low if wdi remains either high or low for longer than the watchdog timeout period. wdo is set high by the next transition at wdi. wdo remains high if wdi is unconnected. 15 reset logic output. reset goes low if v cc falls below the reset threshold. it remains low for 200 ms typ after v cc goes above the reset threshold. 16 reset logic output. reset is an open-drain output. it is the inverse of reset . pin configurations v batt ce in osc in osc sel batt on low line v out ce out reset reset pfo wdi v cc wdo gnd pfi 14 13 12 11 16 15 10 9 8 1 2 3 4 7 6 5 top view (not to scale) adm691a adm693a adm800l adm800m
adm691a/adm693a/adm800l/m C5C rev. 0 typical performance curvesC temperature ? c ?0 125 ?5 0 25 50 75 100 100 20 v cc supply current ?? 70 40 30 90 80 60 50 figure 2. i cc vs. temperature: normal operation temperature ? c ?0 90 ?0 ?0 10 30 50 70 60 30 battery supply current ?na 45 40 35 55 50 figure 3. i batt vs. temperature: battery backup mode temperature ? c ?0 125 ?5 0 25 50 75 100 80 20 ce on resistance ? w 50 40 30 70 60 figure 4. chip enable on-resistance vs. temperature temperature ? c ?0 90 ?0 ?0 10 30 50 70 1.2 0.6 v cc to v out on resistance ?r 0.9 0.8 0.7 1.1 1.0 figure 5. v cc to v out on-resistance vs. temperature i out ?ma 80 0 40 120 v cc to v out ?mv 60 80 100 70 40 30 20 10 60 50 r out = 0.67 w figure 6. v cc to v out voltage drop vs. current i out ?ma 70 0 410 v batt to v out ?mv 68 60 50 40 20 10 30 r out = 7 w figure 7. v batt to v out voltage drop vs. current
adm691a/adm693a/adm800l/m C6C rev. 0 v cc ?v 0 5.0 0.5 1.0 1.5 2.0 2.5 3.0 10 0 i batt ?? 7 2 1 9 8 6 5 4 3 3.5 4.0 4.5 v batt = 2.8v figure 8. battery current vs. input supply voltage c osc ?pf 100 10 0.1 10 1k 100 watchdog and reset timeout period ?s 1 long watchdog timeout period short watchdog timeout period reset active timeout period = > figure 9. watchdog and reset timeout period vs. osc in capacitor temperature ? c ?0 125 ?5 0 25 50 75 100 7.0 4.0 propagation delay ?ns 5.5 5.0 4.5 6.5 6.0 figure 10. chip enable propagation delay vs. temperature load capacitance ?pf 0 300 50 100 150 200 250 16 0 10 4 2 14 12 8 6 propagation delay ?ns figure 11. chip enable propagation delay vs. load capacitance temperature ? c ?0 90 ?0 ?0 10 30 50 70 230 170 reset delay ?ms 200 220 210 190 180 figure 12. reset timeout relay vs. temperature temperature ? c ?0 130 ?0 10 40 70 100 1200 0 reset output resistance ? w 600 1000 800 400 200 v cc = 5v, v batt = 2.8v sourcing current v cc = 0v, v batt = 2.8v sinking current figure 13. reset output resistance vs. temperature
adm691a/adm693a/adm800l/m C7C rev. 0 10 0% 100 90 400ms 1v figure 14. reset output voltage vs. supply 10 0% 100 90 10? 1v figure 15. reset response time power fail reset output reset is an active low output that provides a reset signal to the microprocessor whenever v cc is at an invalid level. when v cc falls below the reset threshold, the reset output is f orced low. the reset voltage threshold is 4.65 v (adm691a/ adm800l) or 4.4 v (adm693a/adm800m). on power-up reset will remain low for 200 milliseconds after v cc rises above the appropriate reset threshold. this allows time for the power supply and microprocessor to stabilize. on power- down, the reset output remains low with v cc as low as 1 v. this ensures that the microprocessor is held in a stable shut- down condition. if reset is required to be low for voltages be- low 1 v, this may be achieved by connecting a pull-down resistor on the reset line. the resistor will help maintain reset low down to v cc = 0 v. note that this is only necessary if v batt is below 2 v. with battery voltages 3 2 v reset will function cor- rectly with v cc from 0 v to +5.5 v. this reset active time is adjustable by using an external oscillator or by connecting an external capacitor to the osc in pin. refer to table ii. the guaranteed minimum and maximum thresholds of the adm691a/adm800l are 4.5 v and 4.75 v, while the guaran- teed thresholds of the adm693a/adm800m are 4.25 v and 4.5 v. the adm691a/adm800l is therefore compatible with 5 v supplies with a +10%, C5% tolerance while the adm693a/ adm800m is compatible with 5 v 10% supplies. in addition to reset an active high reset output is provided. this is the complement of reset and is useful for processors requiring an active high reset signal. watchdog timer reset the watchdog timer circuit monitors the activity of the micro- processor in order to check that it is not stalled in an indefinite loop. an output line on the processor is used to toggle the watchdog input (wdi) line. if this line is not toggled within the selected timeout period, a reset pulse is generated. the watch- dog timeout period may be configured for either a fixed short 100 ms or a long 1.6 second timeout period or for an adjust- able timeout period. note that even if the short timeout period is selected, the first time out immediately following a reset is 1.6 sec. this is to allow additional time for the microprocessor to regain control following a reset. the watchdog timer is restarted at the end of reset, whether the reset was caused by lack of activity on wdi or by v cc falling be- low the reset threshold. the normal (short) timeout period becomes effective following the first transition of wdi after reset has gone inactive. the watchdog timeout period restarts with each transition on the wdi pin. to ensure that the watchdog timer does not time out, either a high-to-low or low-to high transition on the wdi pin must occur at or less than the minimum timeout period. if wdi remains permanently either high or low, reset pulses will be is- sued after each timeout period (1.6 seconds). the watchdog monitor can be deactivated by floating the watchdog input (wdi). if floating, an internal resistor network biases wdi to around 1.6 v. chip enable output control v batt v cc ce in osc in osc sel watchdog input (wdi) power fail input (pfi) 1 voltage detector = 4.4v (adm693a/adm800m) adm691a/adm693a adm800l/adm800m 1.25v watchdog transition detector watchdog timer reset & watchdog timebase reset & generator 4.65v 1 batt on low line v out ce out reset reset watchdog output ( wdo ) power fail output ( pfo ) figure 16. functional block diagram watchdog output ( wdo ) the watchdog output wdo provides a status output that goes low if the watchdog timer times out and remains low until set high by the next transition on the watchdog input. wdo is also set high when v cc goes below the reset threshold. if wdi re- mains high or low indefinitely, reset and reset will gener- ate 200 ms pulses every 1.6 sec.
adm691a/adm693a/adm800l/m C8C rev. 0 changing the watchdog and reset timeout the watchdog and reset timeout periods may be controlled us- ing osc sel and osc in. please refer to table ii. with both these inputs floating (or connected to v out ) as in figure 16, the reset timeout is fixed at 200 ms and the watchdog timeout is fixed at 1.6 sec.. if osc in is connected to gnd as in figure 16, the reset timeout period remains at 200 ms but a short (100 ms) watchdog timeout period is selected (except immedi- ately following a reset where it reverts to 1.6 sec). by connecting osc sel to gnd it is possible to select alternative timeout pe- riods by either connecting a capacitor from osc in to gnd or by overdriving osc in with an external clock. with an external capacitor, the watchdog timeout period is twd ( ms ) = 600 ( c /47 pf ) and the reset active period is treset ( ms ) = 1200 (c/47 pf ) with an external clock connected to osc in, the timeout periods become twd = 1024 (1/ f clk ) treset = 2048 (1/ f clk ) battery-switchover section during normal operation with v cc higher than the reset thresh- old and higher than v batt , v cc is internally switched to v out via an internal pmos transistor switch. this switch has a typi- cal on-resistance of 0.75 w and can supply up to 250 ma at the v out terminal. v out is normally used to drive a ram memory bank which may require instantaneous currents of greater than 250 ma. if this is the case then a bypass capacitor should be connected to v out . the capacitor will provide the peak current transients to the ram. a capacitance value of 0.1 m f or greater may be used. if the continuous output current requirement at v out exceeds 250 ma or if a lower v cc Cv out voltage differential is desired, an external pnp pass transistor may be connected in parallel with the internal transistor. the batt on output can drive the base of the external transistor. if v cc drops below v batt and below the reset threshold, battery backup is selected. a 7 w mosfet switch connects the v batt input to v out . this mosfet has very low input-to-output differen tial (dropout voltage) at the low current levels required for battery backup of cmos ram or other low power cmos cir- cuitry. the supply current in battery backup is typically 0.04 m a. high value capacitors, either standard electrolytic or the farad- size double layer capacitors, can also be used for short-term memory backup. if the battery-switchover section is not used, v batt should be connected to gnd and v out should be connected to v cc . when v cc is below the reset threshold, the watchdog function is disabled and wdi goes high impedance as it is disconnected from its internal resistor network. the internal oscillator is enabled when osc sel is high or floating. in this mode, osc in selects between the 1.6 second and 100 ms watchdog timeout periods. ce in reset reset v cc ce out osc sel reset threshold 80? t rs 12? t rs 80? figure 17. reset and chip enable timing osc sel osc in 7 8 adm69_a adm800_ clock 0 to 250khz figure 18a. external clock source osc sel osc in 7 8 adm69_a adm800_ nc nc figure 18b. internal oscillator (1.6 s watchdog) 7 osc sel osc in 8 adm69_a adm800_ c osc figure 18c. external capacitor table ii. reset pulse width and watchdog timeout selections watchdog timeout period osc sel osc in normal immediately after reset reset active period low external clock input 1024 clks 4096 clks 2048 clks low external capacitor 600 ms c/47 pf 2.4 s c/47 pf 1200 ms c/47 pf floating low 100 ms 1.6 s 200 ms floating floating or v out 1.6 s 1.6 s 200 ms
adm691a/adm693a/adm800l/m C9C rev. 0 7 osc sel osc in 8 adm69_a adm800_ c osc figure 18d. internal oscillator (100 ms watchdog) wdi wdo t 1 reset t 1 = reset time. t 2 = normal (short) watchdog timeout period. t 3 = watchdog timeout period immediately following a reset. t 1 t 1 t 2 t 3 figure 19. watchdog timing ce gating and ram write protection all products include memory protection circuitry which ensures the integrity of data in memory by preventing write operations when v cc is at an invalid level. there are two additional pins, ce in and ce out , that control the chip enable or write inputs of cmos ram. when v cc is present, ce out is a buffered rep- lica of ce in , with a 5 ns propagation delay. when v cc falls be- low the reset voltage threshold, an internal gate forces ce out high, independent of ce in . ce out typically drives the ce, cs, or write input of battery backed up cmos ram. this ensures the integrity of the data in memory by preventing write operations when v cc is at an in- valid level. similar protection of eeproms can be achieved by using the ce out to drive the store or write inputs of an eeprom, earom, or novram. power fail warning comparator an additional comparator is provided for early warning of fail- ure in the microprocessors power supply. the power fail input (pfi) is compared to an internal +1.25 v reference. the power fail output ( pfo ) goes low when the voltage at pfi is less than 1.3 v. typically pfi is driven by an external voltage divider that senses either the unregulated dc input to the systems 5 v regu- lator or the regulated 5 v output. the voltage divider ratio can be chosen such that the voltage at pfi falls below 1.25 v several milliseconds before the +5 v power supply falls below the reset threshold. pfo is normally used to interrupt the microprocessor so that data can be stored in ram and the shut- down proce- dure executed before power is lost. r2 pfo 1.25v power fail input power fail output r1 input power figure 20. power fail comparator table iii. input and output status in battery backup mode signal status v batt supply current is <1 m a. v out v out is connected to v batt via an internal pmos switch. v cc switchover comparator monitors v cc for active switchover. gnd 0 v. batt on logic high. the open circuit voltage is equal to v out . low line logic low. osc in osc in is ignored. osc sel osc sel is ignored. pfi the power fail comparator remains active in the battery-backup mode for v cc 3 v batt C1.2 v. with v cc lower than this, pfo is forced low. pfo the power fail comparator remains active in the battery-backup mode for v cc 3 v batt C1.2 v. with v cc lower than this, pfo is forced low. wdi wdi is ignored. ce out logic high. the open circuit voltage is equal to v out . ce in high impedance. wdo logic high. the open circuit voltage is equal to v out . reset logic low. reset high impedance.
adm691a/adm693a/adm800l/m C10C rev. 0 applications information increasing the drive current if the continuous output current requirements at v out exceeds 250 ma or if a lower v cc Cv out voltage differential is desired, an external pnp pass transistor may be connected in parallel with the internal transistor. the batt on output can drive the base of the external transistor via a current limiting transistor. 0.1? +5v input power v cc batt on v batt battery pnp transistor v out 0.1? figure 21. increasing the drive current using a rechargeable battery for backup if a capacitor or a rechargeable battery is used for backup, then the charging resistor should be connected to v out since this eliminates the discharge path that would exist during power down if the resistor were connected to v cc. rechargeable battery v out ?v batt r i = r adm69_a adm800_ 0.1? +5v input power v cc v batt v out 0.1? figure 22. rechargeable battery adding hysteresis to the power fail comparator for increased noise immunity, hysteresis may be added to the power fail comparator. since the comparator circuit is noninverting, hyst eresis can be added simply by connecting a resistor between the pfo output and the pfi input as shown in figure 23. when pfo is low, resistor r3 sinks current from the summing junction at the pfi pin. when pfo is high, r3 sources current into the pfi summing junction. this results in differing trip levels for the comparator. resistors r1 and r2 therefore set the trip point while r3 adds hysteresis. r3 should be larger than 10 k w so that it does not cause excessive loading on the pfo output. addi- tional noise rejection and filtering may be achieved by adding a capacitor from pfi to gnd. 1.25v (pfo) input power r1 r2 pfi r3 to ? nmi 5v pfo 0v 0v v l v m v in v h = 1.25 1 + r 1 r 2 +r 3 r 2 r 3 v l = 1 .25 +r 1 1.25 v cc 1.25 r 2 r 3 v mid = 1.25 r 1 +r 2 r 2 figure 23. adding hysteresis to the power fail comparator typical operating circuit a typical operating circuit is shown in figure 24. the circuit features power supply monitoring, battery backup switching and watchdog timing. cmos ram is powered from v out . when 5 v power is present, this is routed to v out . if v cc fails, then v batt is routed to v out . v out can supply up to 250 ma from v cc , but if more current is required, an external pnp transistor can be added. when v cc is higher than v batt and the reset threshold, batt on goes low, providing base drive for the external tran- sistor. when v cc is lower than v batt and the reset threshold, an internal 7 w . mosfet connects the backup battery to v out . reset output the internal voltage detector monitors v cc and generates a reset output to hold the microprocessors reset line low when v cc is below the reset threshold. an internal timer holds reset low for 200 ms after v cc rises above the threshold. this prevents repeated toggling of reset even if the 5 v power drops out and recovers with each power line cycle. early power fail detector the input power line is monitored via a resistive potential di- vider connected to the power fail input (pfi). when the volt- age at pfi falls below 1.25 v, the power fail output ( pfo ) drives the processors nmi input low. if a power fail threshold of 7 v is set with resistors r1 and r2, the microprocessor will have the time when v cc drops below 7 v to save data into ram. power supply capacitance will extend the time available. this will allow more time for microprocessor housekeeping tasks to be completed before power is lost.
adm691a/adm693a/adm800l/m C11C rev. 0 ram write protection the ce out line drives the chip select inputs of the cmos ram. ce out follows ce in as long as v cc is above the reset threshold. if v cc falls below the reset threshold, ce out goes high, independent of the logic level at ce in . this prevents the microprocessor from writing erroneous data into ram during power-up, power-down, brownouts and momentary power in- terruptions. the low line output goes low when v cc falls below the reset threshold. watchdog timer the microprocessor drives the watchdog input (wdi) with an i/o line. when osc in and osc sel are uncon- nected, the microprocessor must toggle the wdi pin once every 1.6 seconds to verify proper software execution. if a hardware or software failure occurs such that wdi not toggled a 200 ms reset pulse will be generated after 1.6 seconds. this typi- cally restarts the microprocessors power-up routine. a new reset pulse is issued every 1.6 seconds until wdi is again strobed. the watchdog output ( wdo ) goes low if the watch- dog timer is not serviced within its timeout period. once wdo goes low it remains low until a transition occurs at wdi. the watchdog timer feature can be disabled by leaving wdi uncon- nected. osc in and osc sel also allow other watchdog tim- ing options. reset also goes low if the watchdog timer is enabled and wdi remains either high or low for longer than the watchdog timeout period. the reset output has an internal 1.6 ma pullup, and can ei- ther connect to an open collector reset bus or directly drive a cmos gate without an external pullup resistor. 3v battery 0.1? 0.1? osc in osc sel gnd pfi nc 0.1? reset wdo low line system status indicators reset pfo wdi ce in ce out v batt r2 r1 cmos ram address decode input power +5v v cc batt on v out a0?15 i/o line nmi reset p adm691a adm693a adm800l adm800m figure 24. typical application circuit
adm691a/adm693a/adm800l/m C12C rev. 0 outline dimensions dimensions shown in inches and (mm). c2198C12C10/96 printed in u.s.a. 16-lead plastic dip (n-16) 16 18 9 0.840 (21.33) 0.745 (18.93) 0.280 (7.11) 0.240 (6.10) pin 1 seating plane 0.022 (0.558) 0.014 (0.356) 0.060 (1.52) 0.015 (0.38) 0.210 (5.33) max 0.130 (3.30) min 0.070 (1.77) 0.045 (1.15) 0.100 (2.54) bsc 0.160 (4.06) 0.115 (2.93) 0.325 (8.25) 0.300 (7.62) 0.015 (0.381) 0.008 (0.204) 0.195 (4.95) 0.115 (2.93) 16-lead wide soic (r-16w) 16 9 8 1 0.4133 (10.50) 0.3977 (10.00) 0.4193 (10.65) 0.3937 (10.00) 0.2992 (7.60) 0.2914 (7.40) pin 1 seating plane 0.0118 (0.30) 0.0040 (0.10) 0.0192 (0.49) 0.0138 (0.35) 0.1043 (2.65) 0.0926 (2.35) 0.0500 (1.27) bsc 0.0125 (0.32) 0.0091 (0.23) 0.0500 (1.27) 0.0157 (0.40) 8 0 0.0291 (0.74) 0.0098 (0.25) x 45 16-lead tssop (ru-16) 16 9 8 1 0.201 (5.10) 0.193 (4.90) 0.256 (6.50) 0.246 (6.25) 0.177 (4.50) 0.169 (4.30) pin 1 seating plane 0.006 (0.15) 0.002 (0.05) 0.0118 (0.30) 0.0075 (0.19) 0.0256 (0.65) bsc 0.0433 (1.10) max 0.0079 (0.20) 0.0035 (0.090) 0.028 (0.70) 0.020 (0.50) 8 0 16-lead narrow soic (r-16n) 16 9 8 1 0.3937 (10.00) 0.3859 (9.80) 0.2550 (6.20) 0.2284 (5.80) 0.1574 (4.00) 0.1497 (5.80) pin 1 seating plane 0.0098 (0.25) 0.0040 (0.10) 0.0192 (0.49) 0.0138 (0.35) 0.0688 (1.75) 0.0532 (1.35) 0.0500 (1.27) bsc 0.0099 (0.25) 0.0075 (0.19) 0.0500 (1.27) 0.0160 (0.41) 8 0 0.0196 (0.50) 0.0099 (0.25) x 45

▲Up To Search▲

Price & Availability of ADM800MARNZ

	To Download ADM800MARNZ Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .